Low-Dropout Regulator IC
VLSI Design Project
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Introduction
This project is a full custom-analog design of a 1.2 V low-dropout regulator implemented in the SkyWater 130 nm process. I designed the complete signal chain, bandgap reference, error amplifier, PMOS pass transistor, and iterated through transistor sizing, biasing, compensation, and corner-aware verification to achieve a stable regulator with load regulation and transient behavior. The design was validated with pre-layout simulations and then brought through transistor-level layout in Cadence Virtuoso, where I closed the loop with DRC/LVS signoff and post-layout extracted performance checks.
The regulator uses a bandgap reference to generate a stable VREF across supply and temperature variation. A two-stage CMOS operational amplifier compares a scaled version of VOUT to VREF and drives the gate of a PMOS pass device, modulating channel resistance to regulate the output. Stability was ensured via frequency compensation and verified using loop gain/phase margin analysis under multiple load and line conditions.
Two-Stage Op-Amp Design
I designed and simulated a two-stage CMOS op-amp optimized for high DC gain and sufficient bandwidth to meet regulation and transient requirements. The first stage provides high gain and input common-mode compatibility in Sky130, while the second stage supplies the necessary swing to drive the PMOS gate. I iterated device sizing and bias currents to balance gain, GBW, output swing, and power, then validated stability by extracting loop response and ensuring adequate phase margin across operating points.
Bandgap Reference
To make the LDO resilient against supply and environmental drift, I implemented a bandgap reference that provides a temperature-compensated VREF suitable for analog regulation. I validated that VREF remains stable under supply variation and then propagated that reference into the full LDO loop to quantify end-to-end regulation performance. This reference block was simulated independently and then integrated into top-level testbenches for line/load sweeps and transient tests.
PMOS Pass Transistor
The LDO uses a PMOS pass transistor as the series element to supply load current while maintaining low dropout. I sized the device to meet worst-case load current at minimum VIN, balancing dropout, RDS(on), and gate capacitance. Since the pass device heavily affects loop dynamics, I included its gate loading in stability checks and verified regulation and transient behavior across line and load conditions, ensuring the error amplifier can drive the gate without saturating.
Cadence Virtuoso Layout
I created full-custom, transistor-level layouts in Cadence Virtuoso for the op-amp, bandgap, and pass device interface using analog layout best practices such as device matching, careful routing of sensitive nodes, guard rings, and reduced parasitic coupling. I ran DRC to confirm design-rule compliance and LVS to verify schematic-to-layout equivalence. After parasitic extraction, I repeated key performance simulations including regulation, transient response, and PSRR to confirm the design remained tapeout-ready under post-layout conditions.
Verification
I verified the full regulator using structured simulation testbenches, checking:
Line regulation: VOUT response to supply sweeps
Load regulation: VOUT response to load current changes
Load transient: step-load events to evaluate undershoot/overshoot and settling
PSRR: frequency sweep of supply ripple injection to quantify rejection
Stability: loop gain and phase margin across operating conditions
This verification was performed both pre-layout and again post-layout extracted, ensuring parasitics did not destabilize the loop or degrade transient response beyond acceptable limits.
Overall, this project demonstrates an end-to-end custom analog IC workflow, from architecture and transistor-level design through verification, full-custom layout, and post-layout validation in SkyWater 130 nm. By closing DRC/LVS and confirming regulation, transient response, stability, and PSRR after extraction, I ensured the LDO is ready for tapeout-level requirements and can serve as a strong foundation for future power-management blocks.
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