Low-Dropout Regulator IC

I designed a full-custom 1.2 V low-dropout regulator in the SkyWater 130 nm process using Cadence Virtuoso. The design integrates a bandgap reference, a two-stage CMOS error amplifier, a resistive feedback network, and a PMOS pass device. I designed and simulated the major blocks individually before integrating them into a closed-loop regulator. After completing pre-layout verification, I created transistor-level layouts for the main circuit blocks, ran design-rule checking and schematic-versus-layout verification, and evaluated the effect of extracted parasitics through post-layout simulation.

The goal of the project was to maintain a stable 1.2 V output across changes in input voltage and load current while preserving adequate loop stability and transient response. The project required balancing DC gain, bandwidth, device sizing, bias current, dropout voltage, compensation, and layout parasitics.

The bandgap reference generates a stable reference voltage for the regulator. A feedback divider produces a scaled representation of the output voltage, which is compared with the reference by the error amplifier. The amplifier then adjusts the gate voltage of the PMOS pass device. Through negative feedback, the pass device changes the current delivered to the load until the feedback voltage returns to the reference level and the output settles near its target value.

I designed a two-stage CMOS error amplifier to provide the DC gain and output swing required by the regulator loop. The input stage was sized for the required input common-mode range and gain within the SkyWater 130nm device limits. The second stage provides additional gain and drives the capacitance at the PMOS gate. I iterated transistor dimensions and bias currents to balance DC gain, unity-gain bandwidth, phase margin, output swing, and power consumption.

I implemented a bandgap reference to establish a consistent reference voltage for analog regulation. I simulated the reference independently before integrating it into the complete LDO. Supply and temperature sweeps were used to evaluate how the reference changed across the intended operating range, and the integrated reference was then used in the top-level regulation, transient, and stability testbenches.

The PMOS pass transistor serves as the series element that supplies current to the load while operating with limited voltage headroom. I sized the device to support the required load current at the minimum input voltage while considering dropout voltage, on-resistance, gate capacitance, layout area, and the drive capability of the error amplifier. The feedback-divider ratio was selected so that the closed-loop regulator produced the target 1.2 V output.

The PMOS gate capacitance, output pole, load current, and output capacitance all influence the regulator loop. I used frequency compensation to control the loop response and evaluated loop gain and phase across the intended operating conditions. Stability was checked at multiple load conditions to confirm that the error amplifier could drive the pass device without introducing excessive ringing or oscillation.

I created full-custom transistor-level layouts in Cadence Virtuoso for the error amplifier, voltage reference, and pass-device interface. The layout incorporated device matching, fingered devices, body contacts, guard rings, and careful routing of sensitive analog nodes. Wider metal and multiple vias were used where appropriate for high-current paths and low-resistance connections.

I ran design-rule checking to identify physical-rule violations and schematic-versus-layout verification to confirm that the extracted connectivity matched the intended schematic. I then performed post-layout simulations using the extracted views to evaluate how routing resistance and parasitic capacitance affected regulation, stability, and transient behavior.

I evaluated line regulation by sweeping the input supply and observing the resulting change in output voltage. Load regulation was evaluated by sweeping the load current across the intended operating range. For transient verification, I applied step changes in load current and measured the output undershoot, overshoot, and settling behavior.

I also evaluated loop gain and phase margin to verify closed-loop stability and performed power-supply rejection simulations to measure how effectively the regulator attenuated ripple from the input supply. These tests were performed before layout and repeated with extracted views so that the effect of parasitic resistance and capacitance could be compared directly.

This project demonstrates an end-to-end custom analog IC workflow in the SkyWater 130nm process, including circuit architecture, transistor-level design, block integration, simulation, full-custom layout, physical verification, and post-layout analysis. It gave me practical experience balancing electrical performance with device sizing, compensation, layout parasitics, and physical-design constraints while developing a complete low-dropout regulator.